The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the sub-20 nm node).
A shift to all-digital phase-locked loops (ADPLLs) has accompanied the shrinking of the semiconductor process node. The ADPLL replaces analog components of analog PLLs with digital components, and in some cases, adopts a different architecture completely. One component common to many ADPLL architectures is a time-to-digital converter, or TDC. The TDC converts time information to a coded digital signal. In general, doubling TDC resolution can improve phase noise of the ADPLL by 6 dbC/Hz. Improved resolution also increases jitter measurement circuit accuracy.